产品详细

NUVOTON > ARM9 Family > N3290 MJPEG 系列

    N3290 MJPEG 系列

    新唐的N3290 MJPEG系列,为主频最高可支持到200 MHz的ARM926EJ-S处理器。N3290系列整合了硬件JPEG编解码器,主要应用为低阶视频学习机、婴儿视频监护器、无线网络摄影机和人机界面。N3290系列提供了内建2MB、8MB和32MB不同内存容量且pin脚兼容的64-pin LQFP和128-pin LQFP两种封装。N3290也可当作通用型处理器,使用于各种不同的应用领域。

    Part No. Raw NAND I/F, ECC bits NAND Flash, No. of ECC bits CPU Max Speed I Cache D Cache SRAM Stacked SDRAM (bit) SPI Flash I/F SD / SDIO 1.1 Host (12 Mbps) USB 2.0 Host (480 Mbps) Device (FS / HS) 2D GFX JPEG Codec Video Codec RGB Color (bits) Max. Resolution SAR ADC 24-bit Σ-Δ ADC ADC for MIC Input Touch Panel (Wire) Stereo DAC (bits) JTAG Ethernet 10/100 MAC CMOS Sensor1 GPIO (Max) UART I2C SPI RTC PWM TV Output I2S Core Voltage (V) I/O Voltage (V) Package Status I/O I2S/ AC97 ADC Operating Temp. Range (°C ) SDRAM NOR Flash SPI Flash, No. of I/O Pins ATAPI USB 2.0 HS Device 2D Graphics TFT LCD Speed (Samples per second) Touch Screen Controller LVD/LVR External Bus Interface KPI PS2 PCI Master
    N32901R1DN 15   926 200 MHz 8K 8K 8K 1Mx16 SDR Y 1(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps)     Y   Y   16     Y(CCIR601 / CCIR656 I/F, 2M pixel) 34 2 Y 2(Only one hardware SPI controller to support two SPI device with two chip selection signals)   2   Y 1.8 3.3 LQFP-64 (MCP) Mass Production                                    
    N32901U1DN 15   926 200 MHz 8K 8K 8K 1Mx16 SDR Y 3(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 QVGA(320x240) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 64 2 Y 2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4   Y 1.8 3.3 LQFP-128 (MCP) Mass Production                                    
    N32901U2DN 15   926 200 MHz 8K 8K 8K 1Mx16 SDR Y 2(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 QVGA(320x240) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 59 2   2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4 Y   1.8 3.3 LQFP-128 (MCP) Mass Production                                    
    N32903R1DN 15   926 200 MHz 8K 8K 8K 4Mx16 DDR Y 1(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps)     Y   Y   16     Y(CCIR601 / CCIR656 I/F, 2M pixel) 34 2 Y 2(Only one hardware SPI controller to support two SPI device with two chip selection signals)   2   Y 1.8 3.3 TQFP-64 (MCP) Mass Production                                    
    N32903U1DN 15   926 200 MHz 8K 8K 8K 4Mx16 DDR Y 3(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 VGA(640x480) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 64 2 Y 2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4   Y 1.8 3.3 LQFP-128 (MCP) Mass Production                                    
    N32903U2DN 15   926 200 MHz 8K 8K 8K 4Mx16 DDR Y 2(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 VGA(640x480) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 59 2   2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4 Y   1.8 3.3 LQFP-128 (MCP) Mass Production                                    
    N32905U1DN 15   926 200 MHz 8K 8K 8K 16Mx16 DDR Y 3(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 VGA(640x480) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 64 2 Y 2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4   Y 1.8 3.3 LQFP-128 (MCP) Mass Production                                    
    N32905U2DN 15   926 200 MHz 8K 8K 8K 16Mx16 DDR Y 2(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 VGA(640x480) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 59 2   2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4 Y   1.8 3.3 LQFP-128 (MCP) Mass Production